1. Field of the Invention
The invention relates to the manufacturing of a semiconductor device having an interconnect like a through-wafer via or through-silicon via.
2. Background Art
DE 10 2008 033 395 A1 describes a method for the manufacture of a semiconductor component, in which a semiconductor substrate is provided with a buried insulation layer and a connection pad is arranged in the insulation layer. An opening is created reaching from a top side of the substrate down to the insulation layer above the connection pad. A dielectric layer is deposited, and the dielectric layer and the insulation layer are removed within the opening, so that a dielectric side wall spacer is formed and the connection pad is uncovered. A metallization is deposited in electrical contact with the connection pad and forms an electrical interconnect through the substrate.
In semiconductor technology an etch stop layer is used to define the end of an etching step. The material of the etch stop layer is preferably selected to be essentially unaffected by the attack of the etchant, or at least the etching rate of the etch stop layer is substantially smaller than the etching rate of the material that is to be removed. An etch stop layer may thus provide at least a partial protection against the attack of an etchant. An etch stop layer may also be used to find a desired end point of an etching process by detecting a change of the chemical composition of the atmosphere within the etch apparatus or reactor. The change is caused by different volatile etch products generated by the chemical reactions of the etchant with the material that is to be etched and with the material of the etch stop layer, respectively. Furthermore it is known in the art that a semiconductor oxide can be removed selectively with respect to a layer formed from a semiconductor nitride, a metal or a polyimide.